module binomial (
	input				clk,
	input 				rst_n,
	input 				enable,
 	input 				model,//0->4 1->6

	input 	[95:0]		data_in,
	
	output	reg	[95:0]	data_out_a,
	output	reg	[95:0]	data_out_b,

	input				read_en,
	output	reg			valid_o
);	
	wire [191:0]	data_out_temp;

	genvar i;

	generate
		for(i=0;i<8;i=i+1)begin:cbd0_7
			cbd_core cbd_core(.enable  (enable),
							  .model   (model),
							  .data_in6(data_in[6*i+5:6*i]),
							  .data_in4(data_in[4*i+3:4*i]),
							  .data_out(data_out_temp[12*i+11:12*i]));
		end
	endgenerate

	generate
		for(i=0;i<8;i=i+1)begin:cbd8_15
			cbd_core cbd_core(.enable  (enable),
							  .model   (model),
							  .data_in6(data_in[48+6*i+5:48+6*i]),
							  .data_in4(data_in[32+4*i+3:32+4*i]),
							  .data_out(data_out_temp[96+12*i+11:96+12*i]));
		end
	endgenerate
	
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			data_out_a <= 96'b0;
		else if(read_en)
			data_out_a <= data_out_temp[95:0];
		else
			data_out_a <= 96'b0;
	end

	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			data_out_b <= 96'b0;
		else if(read_en)
			data_out_b <= data_out_temp[191:96];
		else
			data_out_b <= 96'b0;
	end

	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			valid_o <= 1'b0;
		else if(~enable)
			valid_o <= 1'b0;
		else
			valid_o <= read_en;
	end



endmodule